The present invention generally relates to the production test requirement for timing delay fault (TDF) testing for RapidChip and ASIC devices.
In order to meet expectations for shipped product quality levels, the traditional stuck-at fault testing is no longer adequate to reach those quality levels. As such, TDF testing has become a requirement for any and all product applications for which product quality is of utmost concern, e.g. storage components. During TDF testing, a very fast clock pulse is provided to a device-under-test (DUT). The specific problem seen with TDF testing is that most current production test systems cannot exceed a 200 Mhz effective TDF test rate. With 130 nm technology being widely used, and 90 nm technology on the horizon, the 200 Mhz test rate is not adequate to detect TDF-type failures. A higher speed solution is needed on these existing tester platforms, without having to spend significant capital resources to upgrade to newer tester platforms.
One existing solution to the aforementioned problem is to purchase newer tester platforms (i.e., expensive ATE) that can support test frequencies well beyond the current 200 Mhz limitation. However, the capital expenditures required to implement such a solution render the approach infeasible.
Another possible solution would be to utilize on-chip PLL circuitry to create the high-speed clock pulse pair required for the TDF launch/capture clocks. However, this approach is very limited with respect to its flexibility of use on the design, characterization of the maximum TDF operational speed, and being able to test multiple clock domains/frequencies on a single device. Hence, on-chip PLL circuitry is not generally used for TDF testing.